The present invention relates to a ring oscillator incorporated in a semiconductor integrated circuit (LSI) and a method of measuring the gate delay time in this ring oscillator.
As shown in FIG. 1, a conventional ring oscillator is constituted by connecting an odd number of inverters IV101, IV102, . . . , IV123, IV124, and IV125 in a ring shape. An oscillation output is obtained from the output node of an arbitrary inverter.
As shown in FIG. 2, another conventional ring oscillator is constituted such that a NAND.gate circuit ND101 for controlling start/stop of oscillation is inserted in a ring formed by connecting a plurality (even number) of inverters IV101, IV102, . . . , IV123, and IV124.
In the ring oscillator shown in FIG. 1, letting Y be the state (signal level) at, e.g., a connection point NX, this Y is inverted to Y by the next-stage inverter IV101, and the Y is further inverted to Y by the second next-stage inverter IV102. The signal level is sequentially inverted, and becomes Y at the connection point NX through one round because an odd number of inverters are connected. Through one more round, the signal level becomes the original Y. In this manner, the ring oscillator self-oscillates.
In the ring oscillator shown in FIG. 2, the start/stop of oscillation is controlled by externally inputting an "H"- or "L"-level control signal CNT to the NAND gate circuit ND101. That is, the control signal CNT is first set at "L" level and then changed to "H" level to start oscillation. When the control signal CNT is at "L" level, an output signal from the NAND gate circuit ND101 is fixed at "H" level. Outputs from the odd-numbered inverters IV101, IV103, . . . , IV123 change to "L" level, outputs from the even-numbered inverters IV102, IV104, . . . , IV124 change to "H" level, and the initial states of the output levels of the respective inverters are determined. In this state, the ring oscillator does not oscillate. When the control signal CNT changes to "H" level, the NAND gate circuit ND101 substantially operates as an inverter, and the ring oscillator oscillates like the circuit shown in FIG. 1 in which an odd number (125) of inverters are connected in a ring shape.
However, the ring oscillator having the arrangement shown in FIG. 1 may perform high-order odd-number-fold oscillation because the output states of the inverters IV101 to IV125 are not stable immediate after the power supply is turned on. In the ring oscillator having the arrangement shown in FIG. 2, high-order odd-number-fold oscillation can be prevented unlike the circuit shown in FIG. 1 because oscillation starts after initial setting of the output levels of the inverters IV101 to IV124. However, the ring oscillator shown in FIG. 2 must be externally controlled.
The gate delay value (gate delay time) per inverter as a constituent unit has conventionally been obtained by measuring the oscillation frequency of a ring oscillator having an arrangement like the ones shown in FIGS. 1 and 2. In the ring oscillators shown in FIGS. 1 and 2, since the constituent unit is a static gate inverter, the gate delay value obtained by measuring the oscillation frequency includes only delay information of the static gate, and delay information of a dynamic gate requiring precharge cannot be obtained. In the ring oscillator shown in FIG. 1 in which an odd number of inverters are connected in a ring shape, the gate delay value is difficult to determine upon high-order odd-number-fold oscillation.
If the oscillator is constituted using a delay line instead of the ring oscillator, the gate delay per stage can be measured regardless of the static or dynamic gate. In the oscillator using the delay line, however, the gate delay value is more difficult to measure than in the ring oscillator.